Open AccessSelf‐heating burn‐in pattern generation based on the genetic algorithm incorporated with a BACK‐like procedure
Author(s) -
Cheng Zuolin,
Cui Xiaole,
Cui Xiaoxin,
Lee Chung Len
Publication year - 2015
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2014.0219
Subject(s) - burn in , algorithm , dissipation , computation , genetic algorithm , sequence (biology) , computer science , power (physics) , integrated circuit , automatic test pattern generation , electronic circuit , engineering , reliability engineering , electrical engineering , machine learning , physics , genetics , quantum mechanics , biology , thermodynamics , operating system
In integrated circuit (IC) burn‐in, it is desirable to produce efficient input patterns to assist heating for circuit under test. This study proposes and demonstrates an approach which uses the genetic algorithm incorporating with a BACK‐like procedure to generate the patterns which produce the maximal and/or uniform node transition as well as power dissipation for burn‐in application. A multi‐step strategy is applied in the algorithm, and a transition measure is defined to guide the backtracing of the BACK‐like procedure, improving the efficiency in searching the target patterns. Experimental results show that the approach generates better pattern pairs which produce either the maximal transition count or the maximal power dissipation than that of all the other published results. It is also able to generate the pattern sequence which achieves more uniformly stressing, by 30% improvement statistically, for each gate of the circuit under test. The computation time, because of using a divide‐and‐conquer strategy in this approach, is also reasonable, making it useful in the practical IC burn‐in application.