Open AccessSoft error rate estimation of combinational circuits based on vulnerability analysis
Author(s) -
Raji Mohsen,
Pedram Hossein,
Ghavami Behnam
Publication year - 2015
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
ISSN - 1751-861X
DOI - 10.1049/iet-cdt.2014.0157
Subject(s) - soft error , benchmark (surveying) , computer science , combinational logic , algorithm , electronic circuit , monte carlo method , speedup , set (abstract data type) , probabilistic logic , fault injection , fault (geology) , transient (computer programming) , computer engineering , logic gate , electronic engineering , parallel computing , mathematics , engineering , statistics , software , artificial intelligence , electrical engineering , geodesy , seismology , geology , geography , programming language , operating system
Nanometer integrated circuits are getting increasingly vulnerable to soft errors and making the soft error rate (SER) estimation an important challenge. In this study, a novel approach is proposed for SER estimation of combinational circuits based on vulnerability analysis. The authors introduce a concept called probabilistic vulnerability window (PVW) which is an inference of necessary conditions for a single event transient (SET) to cause observable errors in the circuit. A proposed computational framework calculates PVWs for all circuit gates in a backward‐traversing algorithm enabling the circuit designers for an accurate and efficient SER estimation. Experimental results show that the proposed approach is 2× faster than the traditional SER estimation methods and keep its efficiency when it is applied for estimating the SER considering various different SET widths while runtime of traditional estimation methods increases in such cases. In addition, results verify the accuracy (average difference of 0.02) and speedup (about four orders of magnitude) of the proposed method when compared with the Monte Carlo‐based fault injection simulation on ISCAS'85 benchmark circuits.