Open AccessVery‐large‐scale integration implementation of a 16‐bit clocked adiabatic logic logarithmic signal processor
Author(s) -
Yemiscioglu Gurtac,
Lee Peter
Publication year - 2015
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2014.0102
Subject(s) - cmos , adiabatic process , adiabatic circuit , logarithm , clock rate , computer science , electronic engineering , 16 bit , signal (programming language) , logic gate , computer hardware , logic synthesis , electrical engineering , embedded system , logic family , engineering , physics , mathematics , mathematical analysis , thermodynamics , programming language
This study describes a low‐power 16‐bit logarithmic signal processor built using clocked adiabatic logic. The circuit has been designed and implemented using an Austria Micro Systems 0.35 μm complementary metal–oxide–semiconductor (CMOS) process. A test device has been fabricated and functionally verified. The processor architecture has an active area of 0.57 mm 2 . Simulation results with this architecture, using clock frequencies up to 100 MHz have confirmed results from other researchers that clocked adiabatic consumes up to ten times less power than conventional CMOS logic.