Open AccessApplication‐oriented cache memory configuration for energy efficiency in multi‐cores
Author(s) -
Silva Bruno de Abreu,
Cuminato Lucas A.,
Delbem Alexandre C.B.,
Diniz Pedro C.,
Bonato Vanderlei
Publication year - 2015
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
ISSN - 1751-861X
DOI - 10.1049/iet-cdt.2014.0091
Subject(s) - cache , computer science , parallel computing , cpu cache , energy consumption , multi core processor , cache algorithms , embedded system , set (abstract data type) , code (set theory) , homogeneous , base (topology) , energy (signal processing) , gate array , field programmable gate array , engineering , mathematical analysis , statistics , physics , mathematics , electrical engineering , thermodynamics , programming language
This study describes and evaluates an automated technique that exploits the potential of heterogeneous multi‐core processor (HMP) systems when customised with respect to the number of cores and L1 cache memory sizes using a field programmable gate array fitted with LEON3 cores at its base. The authors evaluated the real energy consumption of the HMP system tuned for a set of 50 application codes using a data‐mining tool for finding code similarities and selecting HMP configurations. The selected HMP system configuration requires a small cache configuration and consumes less energy when compared to a homogeneous system with the same number of cores and only with a very modest increase in execution time.