Open AccessImproving security in cache memory by power efficient scrambling technique
Author(s) -
Neagu MădălinIoan,
Miclea Liviu,
Manich Salvador
Publication year - 2015
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2014.0030
Subject(s) - scrambling , computer science , cache , overhead (engineering) , embedded system , power consumption , scope (computer science) , side channel attack , computer hardware , power (physics) , computer network , computer security , cryptography , operating system , physics , algorithm , quantum mechanics , programming language
The last decade has recorded an increase in security protocols for integrated circuits and memory systems, because of device specific attacks such as side‐channel monitoring and cold boot and also because sensitive information is stored in such devices. The scope of this study is to propose new security measures which can be applied in memory systems, in order to make the stored data unusable, if retrieved successfully by any type of attack. The security technique uses interleaved scrambling vectors to scramble the data retained in a memory system and employs several dissemination rules. The proposed technique is investigated and assessed from several perspectives, such as power consumption, time performance and area overhead.