Open AccessMultiplier‐less pipeline architecture for lifting‐based two‐dimensional discrete wavelet transform
Author(s) -
Darji Anand,
R. Arun,
Merchant Shabbir Noman,
Chandorkar Arun
Publication year - 2015
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2013.0167
Subject(s) - clock rate , computer science , application specific integrated circuit , frame rate , multiplier (economics) , field programmable gate array , adder , discrete wavelet transform , computer hardware , standard cell , vhdl , pipeline (software) , very large scale integration , cmos , embedded system , electronic engineering , integrated circuit , wavelet , wavelet transform , engineering , artificial intelligence , operating system , economics , macroeconomics , programming language
In this study, the authors present a multiplier‐less, high‐speed and low‐power pipeline architecture with novel dual Z ‐scanning technique for lifting‐based two‐dimensional (2D) discrete wavelet transform (DWT). The proposed architecture is composed of pipeline one‐dimensional row, column processors and five transposing registers. Moreover, it uses 4 N temporal line buffers to process 2D DWT of image with N × N resolution. Multipliers are designed with shift‐and‐add logic to reduce the critical path to one adder. Dual Z ‐scanning method is employed to reduce the transposition buffers and latency. The proposed architecture is superior to the existed architectures in speed, power and hardware utilisation for similar throughput specification. Register transfer logic (RTL) of the proposed design is described using VHDL and synthesised using Xilinx ISE 10.1. The proposed architecture operates at a frequency of 353.107 MHz, when synthesised for Xilinx Virtex‐IV series field programmable gate array. Frame processing rate of 340 frames/second for full high‐definition video can be achieved at this frequency of operation. RTL of the proposed design is synthesised using UMC 180 nm technology complementary metal‐oxide semiconductor (CMOS) standard cell library for application specific integrated circuit (ASIC) implementation. ASIC synthesis of 2D DWT core uses 20 358 logic gates and consumes only 20.83 mW power at 100 MHz frequency.