Open AccessReducing the system standby power of a personal computer
Author(s) -
Huang Te,
Bai YingWen,
Chao ShihKuan
Publication year - 2015
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2013.0137
Subject(s) - standby power , power budget , power (physics) , power management , embedded system , power control , engineering , electric power system , chip , computer science , switched mode power supply , electrical engineering , voltage , physics , quantum mechanics
Most previous low‐power personal computer designs have been either focused on power efficiency improvement or on software power management in the working states. This research aims to reduce the total standby power amount in the off state. The authors accomplish the goal of reducing the power consumption by a wake‐up device which is replaced by a chip with a still lower consumption. The authors redesign the power circuit and cut off the power supply for the unnecessary chips, with the exception of the power needed for the specific chip used to wake up the system. The authors also turn off the power supply of the original power controller chip which is used to control the system's power status. In addition, the authors use another low‐power chip instead of the original one and redesign the power sequence of the system in order to maintain the system's power state while the system's power status controller is turned off. Finally, as the authors use this low‐power chip to manage the standby power source separately by means of the remote wake‐up devices, the authors reduce further the standby power consumption to 4.4 mW in the power‐off state by use of the various wake‐up methods. The total result is an improvement of approximately 99.3%.