Open AccessSingle event transient tolerant frequency divider
Author(s) -
She Xiaoxuan,
Li Ningxi
Publication year - 2014
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2013.0132
Subject(s) - reset (finance) , frequency divider , transient (computer programming) , single event upset , computer science , set (abstract data type) , real time computing , control theory (sociology) , state (computer science) , electronic engineering , algorithm , engineering , telecommunications , power dividers and directional couplers , computer hardware , static random access memory , control (management) , artificial intelligence , financial economics , programming language , operating system , economics
This study presents a single event upset (SEU) tolerant frequency divider that compares the counted number of rising clock edges with the expected value. The number of counted rising edges being less than expected generally implies that the state is corrupted resulting in faulty output, so the faulty frequency divider is reset to a proper state to correct errors. The number of counted rising edges being greater than expected generally implies that the output is corrupted by a single event transient (SET) without changing the state, hence SET tolerance does not require a reset. Simulation and experimental results demonstrate that the proposed scheme can achieve high operational clock frequency and good SEU hardening capability.