Open AccessReducing the input test data volume under transparent scan
Author(s) -
Pomeranz Irith
Publication year - 2014
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
ISSN - 1751-861X
DOI - 10.1049/iet-cdt.2013.0067
Subject(s) - scan chain , boundary scan , set (abstract data type) , computer science , test set , scan line , automatic test pattern generation , sequential logic , algorithm , electronic circuit , artificial intelligence , integrated circuit , logic gate , engineering , pixel , electrical engineering , grayscale , programming language , operating system
Under an approach to test compaction called transparent scan, a scan circuit is considered as a sequential circuit where the scan‐chain inputs and scan‐select input are included in the set of inputs of the circuit. This provides the flexibility to interleave functional and scan clock cycles in arbitrary ways, and enhances the ability of transparent‐scan sequences to detect target faults. These features are used in this study for reducing the input test data volume by using the same scan‐chain input sequences with different scan‐select sequences to define transparent‐scan sequences. The circuits under consideration have a scan chain that includes their state variables, primary inputs and primary outputs. Scan‐chain input sequences are computed based on a given conventional scan‐based test set that includes compacted single‐cycle and two‐cycle test sets for single stuck‐at and transition faults, respectively. The set of scan‐select sequences is fixed. Using the same scan‐chain input sequences for defining several transparent‐scan sequences, with different scan‐select sequences, allows more faults to be detected with the same set of scan‐chain input sequences. This allows the number of scan‐chain input sequences to be reduced compared with the number of tests in the conventional scan‐based test set.