Open AccessA fault‐tolerant core mapping technique in networks‐on‐chip
Author(s) -
Khalili Fatemeh,
Zarandi Hamid R.
Publication year - 2013
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2013.0032
Subject(s) - chip , computer science , core (optical fiber) , embedded system , multi core processor , many core , fault tolerance , parallel computing , distributed computing , telecommunications
This study proposes a fault‐tolerant technique on application mapping and spare core allocation in networks‐on‐chip. The proposed technique sets the place of spare cores among free non‐faulty processing cores, dynamically. Here, dynamically setting means that the places of spare cores are tuned for each application and are not fixed in the platform statically. Some vertices of each application core graph can be known as critical, based on their vulnerabilities, the performance degradation and the energy consumption overheads because of negative impacts of failure recovery. This technique locates the spare cores near to the critical cores. As the main theoretical contribution, the problem of spare core placement and its impression on system fault‐tolerance properties is discussed. Some metrics are investigated to be considered in spare core allocation. The results of 1 000 000 fault injection experiments show that the proposed technique leads to communication energy reductions and performance improvement, compared with related works.