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Temperature control in three‐network on chips using task migration
Author(s) -
Hassanpour Neda,
Hessabi Shaahin,
Hamedani Parisa Khadem
Publication year - 2013
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2013.0016
Subject(s) - scalability , overhead (engineering) , network on a chip , multiprocessing , computer science , chip , interconnection , reliability (semiconductor) , dissipation , three dimensional integrated circuit , system on a chip , thermal management of electronic devices and systems , integrated circuit , embedded system , power (physics) , parallel computing , engineering , computer network , telecommunications , mechanical engineering , physics , quantum mechanics , database , thermodynamics , operating system
Combination of three‐dimensional (3D) IC technology and network on chip (NoC) is an effective solution to increase system scalability and also alleviate the interconnect problem in large‐scale integrated circuits. However, because of the increased power density in 3D NoC systems and the destructive effect of high temperatures on chip reliability, applying thermal management solutions becomes crucial in such circuits. In this study, the authors propose a runtime distributed migration algorithm based on game theory to balance the heat dissipation among processing elements (PEs) in a 3D NoC chip multiprocessor. The objective of this algorithm is to minimise the 3D NoC system's peak temperature, as well as the overhead imposed on chip performance during migration. Owing to the high thermal correlation between adjacent PEs in the same stack in 3D NoCs, the authors model this multi‐objective problem as a cooperative game. The simulation results indicate upto 23 and 27% decrease in peak temperature, for the benchmarks that have the highest communication rate and the largest number of tasks, respectively. This comes at the price of slight migration overhead in terms of power‐delay product.

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