Open AccessSingle‐configuration fault detection in application‐dependent testing of field programmable gate array interconnects
Author(s) -
Nandha Kumar Thulasiraman,
Almurib Haider Abbas F.,
Lombardi Fabrizio
Publication year - 2013
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2012.0117
Subject(s) - gate array , macrocell array , programmable logic array , field programmable gate array , electronic engineering , fault detection and isolation , computer science , engineering , embedded system , logic gate , electrical engineering , logic synthesis , logic family , actuator
This study presents a new method for application testing of field programmable gate array (FPGA) interconnects at run time. This method utilises new features related to the function for the programming of the look up tables (LUTs), the utilisation (by logic activation/deactivation) of the nets in a interconnect configuration as well as the primary (unused) input/outputs (IOs) of the FPGAs. A new LUT programming function is introduced; the proposed method retains the original interconnect configuration and modifies the function of the LUTs using the so‐called 1‐bit sum function (1‐BSF); the 1‐BSF detects all possible stuck‐at and bridging faults (of all cardinalities) by utilising the all zeros’ vector and a walking‐1 test set. As validated by simulation for benchmark circuits (implemented on the Xilinx Virtex4 and Virtex5), the proposed method (with a polynomial time complexity) results in a single test configuration with 100% coverage. These results also show that the proposed method requires a larger number of test vectors and an availability of unused IOs.