Open AccessBuilt‐in‐self‐test technique for diagnosis of delay faults in cluster‐based field programmable gate arrays
Author(s) -
Das Nachiketa,
Roy Pranab,
Rahaman Hafizur
Publication year - 2013
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2012.0111
Subject(s) - field programmable gate array , built in self test , logic block , multiplier (economics) , computer science , embedded system , gate array , digital signal processing , block (permutation group theory) , computer hardware , geometry , mathematics , economics , macroeconomics
The increased circuit complexity of field programmable gate array (FPGA) poses a major challenge in the testing of FPGAs. One of the test challenges is to detect the delay faults in high‐speed circuits. Built‐in‐self‐test (BIST) Technique is an ease solution compared with expensive automatic test equipment. In this work, a BIST structure is proposed to detect the delay faults in the various resources of the FPGA such as multiplier, digital signal processing (DSP) block, look‐up tables etc. and interconnects of FPGA. The authors have also proposed a full‐diagnosable BISTer structure that improves the testing efficiency of the logic BIST. The proposed BISTer structure can diagnose the faulty configurable logic block (CLB), when all the CLBs in the 2 × 3 BIST are faulty. The proposed scheme has been simulated in Xilinx Vertex FPGA, using ISE tool, Jbits3.0 API and XHWI (Xilinx HardWare Interface) and MATLAB7.0. The result shows significant improvement compared with earlier BIST methods.