Power domain management interface: flexible protocol interface for transaction‐level power domain management

Defining a power management solution for a system‐on‐chip imposes the design of a low power architecture composed of multiple power domains and a power management strategy for power domain state control. If these two elements are energy‐efficient, an energy‐efficient power management solution can be obtained. Transaction‐level of modelling allows a rapid exploration of different power management solutions, hence a fast decision‐making of the most energy‐efficient one. The authors’ previous work proposed an abstraction of the unified power format (UPF) standard semantics to enable fast evaluation of different UPF‐like power architectures at transaction‐level (TL). However, a fast evaluation of different power domain management strategies requires a unique and flexible hardware interface to organise transfers of inter‐power‐domain transactions according to a well‐defined protocol. The proposal of a new hardware protocol interface for power domain state management, called power domain management interface (PDMgIF), and its TL simulation model represents the main contribution of this study. This proposal separates functional and power management communications. It represents a potential extension of existing low power standards (such as UPF) that already miss power domain management semantics.The PDMgIF concepts are demonstrated through an audio application TL platform illustrating a high flexibility and reduced overhead of the TL PDMgIF model.