Open AccessPower bumps and through‐silicon‐vias placement with optimised power mesh structure for power delivery network in three‐dimensional‐integrated circuits
Author(s) -
Jang Cheoljon,
Kim Jaehwan,
Ahn Byunggyu,
Chong Jongwha
Publication year - 2013
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
ISSN - 1751-861X
DOI - 10.1049/iet-cdt.2012.0047
Subject(s) - power network design , power (physics) , integrated circuit , through silicon via , three dimensional integrated circuit , electronic engineering , electronic circuit , node (physics) , electrical engineering , power budget , power module , engineering , drop (telecommunication) , computer science , power factor , voltage , wafer , physics , structural engineering , quantum mechanics
Three‐dimensional‐integrated circuits (3D‐ICs) bring new issues for power delivery network design because of larger current density and more complicated power delivery paths compared to 2D‐IC. The power delivery network consists of power bumps, through‐silicon‐vias (TSVs), and power wires. IR‐drop at each node varies with the number and position of power bumps and TSVs. These three power resources affect IR‐drop of 3D‐ICs. In this study, the authors propose power delivery network design methodology to optimise power resources wherease IR‐drop constraint is satisfied. The simulation results show that the proposed method minimises the number of power bumps and TSVs compared to the conventional method.