Tree‐based scheme for reducing shared cache miss rate leveraging regional, statistical and temporal similarities

Cache miss can have a major impact on overall performance of many‐core systems. A miss may result in extra traffic and delay because of coherency messages. This has been reduced in coarse‐grain coherency protocols where only shared misses require a coherency message. Conventional off‐chip methods manage the shared miss rate by relying on reuse histories. However the pertinent memory overhead that comes with reuse histories makes them impractical for on‐chip multi‐processor systems. In this study, a new scheme has been proposed to reduce shared cache miss rate in multi‐processor system‐on‐chips that benefits from novel prefetching techniques to L2 caches from off‐chip memories or other remote L2 caches located on‐chip. In the proposed scheme, the previously proposed Virtual Tree Coherence (VTC) method has been extended to limit block forwarding messages to true sharers within each region. Instead of relying on exact reuse histories, shared regions are searched for regional, temporal and statistical similarities. These similarities are exploited for determining the sharers that should receive the forwarded blocks. The proposed method has been evaluated with Splash‐2 workloads. Simulation results indicate that the proposed method has reduced shared miss count by up to 75%, and improved interconnect traffic by up to 47% compared with VTC.