Open AccessAll‐digital power‐efficient integrating frequency difference‐to‐digital converter for GHz frequency‐locking
Author(s) -
Li Yue,
Yuan Fei
Publication year - 2020
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2020.0039
Subject(s) - cmos , digitally controlled oscillator , electronic engineering , electrical engineering , frequency band , phase locked loop , frequency synthesizer , power (physics) , digital down converter , phase noise , time to digital converter , frequency scaling , frequency multiplier , engineering , computer science , physics , jitter , variable frequency oscillator , voltage , digital signal processing , digital signal , clock signal , quantum mechanics , antenna (radio)
This study presents an all‐digital power‐efficient integrating frequency difference‐to‐digital converter (iFDDC) and explores its applications in gigahertz (GHz) frequency‐locking. The iFDDC utilises a bi‐directional gated delay line (BDGDL) to detect and accumulate the frequency difference between two GHz signals and digitises the result with ultra‐low power consumption. The built‐in integration of the iFDDC ensures that the in‐band quantisation noise of the BDGDL and digital controlled oscillator (DCO) is first‐order suppressed. The all‐digital realisation of the iFDDC makes it fully compatible with technology scaling. The effectiveness of the proposed iFDDC is verified using the simulation results of a 5 GHz frequency‐locked loop designed in a Taiwan Semiconductor Manufacturing Company (TSMC) 65 nm 1.2 V complementary metal‐oxide‐semiconductor (CMOS). The iFDDC consumes only 474 µW, offering the lowest power/frequency efficiency among reported FDDCs. The DCO locks to 5 GHz reference in <10 cycles.