Open AccessFine resolution delay tuning method to improve the linearity of an unbalanced time‐to‐digital converter on a Xilinx FPGA
Author(s) -
Berrima Safa,
Blaquière Yves,
Savaria Yvon
Publication year - 2020
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2020.0026
Subject(s) - field programmable gate array , computer science , linearity , least significant bit , routing (electronic design automation) , differential nonlinearity , computer hardware , embedded system , electronic engineering , engineering , operating system
In this study, a method for fine adjustment of Xilinx field programmable gate array (FPGA) routing delays is proposed and applied to improve the linearity of an unbalanced multi‐measurement time‐to‐digital converter (TDC). The delay control method increases load capacitances of interconnect points of switch matrices by small amounts using additional connections to unused interconnects in the FPGA fabric. The novel delay control method uses the tool command language (TCL) scripting feature available in the Xilinx Vivado tool to automatically add wires into a fully placed and routed design. A total of 61 additional wires were successfully and automatically added to reduce the differential and integral non‐linearities of the target TDC from 0.51 and −0.54 LSB to 0.05 and 0.06 LSB, respectively (reduction factors of 10.2 and 9) for an LSB equal to 333 ps.