Open AccessFast‐locking PLL based on a novel PFD‐CP structure and reconfigurable loop filter
Author(s) -
Abolhasani Alireza,
Mousazadeh Morteza,
Khoei Abdollah
Publication year - 2020
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2019.0561
Subject(s) - phase locked loop , pll multibit , electronic engineering , charge pump , computer science , phase detector , power (physics) , electronic circuit , cmos , electrical engineering , engineering , voltage , phase noise , physics , capacitor , quantum mechanics
In this study, the design routine of a novel phase frequency detector and charge‐pump (PFD‐CP) is discussed. The main advantage of the proposed circuit is its improved dead zone performance as the circuits of PFD‐CP have been merged to reduce the latency of the structure. To justify this, by means of a reconfigurable loop filter, a fast‐locking low‐power phase‐locked loop (PLL) has been implemented which can operate at the range of 100 MHz–1.2 GHz while its power consumption is 2.53 mW at 1.2 GHz operating frequency. The whole PLL is implemented in 0.18 µm complementary metal–oxide–semiconductor technology with a 1.8 V power supply. The post‐layout simulation results are provided to show the conformity of theoretical assumptions and circuit‐level implementations which depict the locking time of 0.54 µs at 1.2 GHz operating frequency.