Open AccessFlexible hardware approach to multi‐core time‐predictable systems design based on the interleaved pipeline processing
Author(s) -
Antolak Ernest,
Pułka Andrzej
Publication year - 2020
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2019.0521
Subject(s) - computer science , embedded system , field programmable gate array , computer architecture , pipeline (software) , verilog , virtex , reduced instruction set computing , architecture , computer hardware , instruction set , operating system , art , visual arts
The study presents a hardware‐based approach to modelling and design of time‐predictable electronic embedded systems. It addresses multithread and multitask problems of contemporary real‐time systems. Authors propose a universal template of the reconfigurable system architectures that can be flexibly accommodated to a given application. The synthesisable and parametrised model of the system architecture has been implemented in VERILOG. The architecture is based on ARM‐like RISC solutions and its heart, the main core, is built of 8–12 stage reconfigurable pipelining with the interleaving mechanism. This core is a basic building block of the system and it can be replicated. Each core can handle several hardware threads with replicated register files. The entire structure has a deadline controlling mechanism that is responsible for tasks' evaluation predictability. The authors analyse the coherency of the proposed memory system and interoperability between hardware threads. Three different static scheduling algorithms have been developed and presented in examples. This study contains the results of the simulation experiments and the summary of the hardware implementation in Virtex‐7 FPGA platforms. Authors have investigated the timing parameters of the system and pointed out the areas for further research.