Open AccessAnalytical drain current model of strained junctionless nanowire tunnel field‐effect transistor fabricated on S i 1 − x G e x virtual substrate
Author(s) -
Zhang Yefei,
Li Zunchao
Publication year - 2020
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2019.0515
Subject(s) - nanowire , substrate (aquarium) , materials science , optoelectronics , field effect transistor , current (fluid) , transistor , field (mathematics) , nanotechnology , engineering physics , electrical engineering , engineering , voltage , geology , oceanography , mathematics , pure mathematics
This study proposes an analytical drain model of the strained junctionless nanowire tunnel field‐effect transistor fabricated on the S i 1 − x G e x virtual substrate. The surface potential is derived by solving Poisson's equation in the channel region. Effects of the strained silicon on the potential profile can be expressed as a function of the Ge concentration in the S i 1 − x G e x virtual substrate. An analytical expression for the drain current is derived by using the tangent line approximation method. The strain induced in the device could reduce the effective tunnelling barrier significantly, resulting in a larger band‐to‐band tunnelling generation rate and, therefore, higher drive current compared with the unstrained device. Impacts of device parameters such as the channel diameter, gate oxide thickness and gate dielectric constant on the device performance are investigated. Results of the proposed model are verified by comparing with the device simulator.