Open Access3D device‐level simulation of charge separation from sidewall in vertical transfer gate pinned photodiode pixels for noise mitigation
Author(s) -
Heidari Sakineh,
Alaibakhsh Hamzeh,
Azim Karami Mohammad
Publication year - 2020
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2019.0501
Subject(s) - photodiode , pixel , noise (video) , materials science , signal (programming language) , triboelectric effect , diffusion , optoelectronics , channel (broadcasting) , cmos , image sensor , optics , transfer (computing) , physics , electrical engineering , computer science , image (mathematics) , engineering , artificial intelligence , composite material , parallel computing , thermodynamics , programming language
This study proposes vertical sidewall implantation for noise reduction of CMOS image sensor pixel employing a vertical transfer gate (VTG). The pixel performance is evaluated by 3D device‐level simulation. It is concluded that the proposed pixel's output is less sensitive to interface traps compared to similar previous work. In previous back‐side‐illuminated shared VTG pixel, which lacks the sidewall implantation for noise mitigation, photogenerated carriers were transferred to the floating diffusion (FD) region along with the interface. In the proposed pixel, the channel is separated from the interface, and photogenerated carriers are transferred with 10 nm distance from VTG. The proposed pixel has a complete charge transfer from the buried pinned photodiode to FD with 1274 e − /µm 2 equilibrium full‐well capacity. The conversion gain is 200 μV/e − and the signal‐to‐noise ratio is 37 dB.