
Digitally programmable modified current differencing transconductance amplifier in 40‐nm technology: design flow, parameter analyses and applications
Author(s) -
Malcher Andrzej,
Kristof Adam,
Pułka Andrzej
Publication year - 2020
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2019.0494
Subject(s) - schematic , computer science , vhdl , electronic engineering , amplifier , transconductance , hardware description language , design flow , cmos , computer hardware , engineering , electrical engineering , field programmable gate array , voltage , embedded system , transistor
The study discusses selected issues of modelling and designing current‐mode devices. The authors propose the design flow that covers abstract behavioural models, the schematic and SPICE‐level netlists and the post‐layout parasitic parameters. The considerations related to the analogue functional blocks with a dual‐stage complexity. The theoretical backgrounds of the current‐mode basic building blocks are introduced. Special attention has been paid to a new current‐mode active component, digitally programmable modified current differencing transconductance amplifier (MCDTA). Based on the idea of an MCDTA, the authors have developed their own cell, which integrates the digital control feature (programmability) into current‐mode analogue devices. This original solution enables the dual control techniques, coarse digital control and precise analogue control to be used. The presented examples of continuous‐time active filters show that such a solution enables flexibility in the digital control of the parameters of analogue blocks. In order to facilitate the integration of the analogue and mixed‐signal models in a single environment, VHSIC Hardware Description Language ‐ Analogue Mixed Signal (VHDL‐AMS) language was selected for the behavioural modelling methodology. The authors have used the back annotating mechanism to update behavioural models based on an estimation of the post‐layout parameters. The approach is presented on examples that were implemented in TMSC 40 nm complementary metal–oxide–semiconductor technology.