Open AccessEvaluation of circuit performance of T‐shaped tunnel FET
Author(s) -
Dubey Prabhat Kumar,
Kaushik Brajesh Kumar
Publication year - 2020
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2019.0456
Subject(s) - spice , inverter , transistor , amplifier , cmos , electrical engineering , electronic engineering , physics , voltage , engineering
This study investigates the analogue performance of a III–V tunnelling field‐effect transistor (TFET). To explore the circuit performance of the TFET, a T‐shaped TFET (TTFET) structure is investigated and its performance parameters are compared with a 14 nm simulation program with integrated circuit emphasis (SPICE)‐based predictive technology model FinFET. The advantages and limitations of TTFET technology over its FinFET counterparts are discussed in detail by implementing the inverter, current mirror, track‐and‐hold (T/H), and differential amplifier circuits. It is observed that the TTFET inverter offers 1.56× higher maximum gain, 14.46× lower delay, and 12.13× lower‐energy‐delay product when compared with FinFET inverter in Fan‐Out1 (FO1) configuration at V DD = 0.3 V. The TTFET‐based current mirror and T/H circuit perform superior to their FinFET counterparts in terms of accuracy and delay. The TTFET‐based differential amplifier provides 24.63 dB higher differential gain and 21.5 dB higher common‐mode rejection ratio when compared with FinFET amplifier. Finally, the impact of the variation in process parameters on the device and circuit performance has been investigated. The standard deviation of 20% in oxide thickness, 20% in channel thickness, 20% in source doping, and 2% in metal work function results in a standard deviation 2.56% in delay of FO1 inverter from its nominal value.