Open AccessDesign of ternary logic gates and circuits using GNRFETs
Author(s) -
Madhuri Badugu Divya,
Sunithamani Subramani
Publication year - 2020
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2019.0427
Subject(s) - pass transistor logic , logic gate , logic family , ternary operation , digital electronics , electronic circuit , resistor–transistor logic , adder , computer science , electronic engineering , logic synthesis , algorithm , electrical engineering , engineering , cmos , programming language
In this study, the design of digital logic gates and circuits in ternary logic is presented. The ternary logic is observed to be a better alternative to the traditional binary logic because it offers faster computations, smaller chip area, and lesser interconnects. Thus, it allows designing the low‐complex, high‐speed, and energy‐efficient circuits in future digital design. A novel technique is proposed to design the ternary logic gates using multi‐threshold graphene nanoribbon field‐effect transistors (GNRFETs). The GNRFET threshold voltage is controlled by the width of the graphene nanoribbon, which is defined by the dimer lines number. Three different inverters are designed namely standard, positive, and negative inverters along with the basic and universal logic gates. Additionally, the ternary half adder and full adder are proposed that further helps to design the complex arithmetic circuits. All the proposed ternary logic circuits have been extensively simulated in SPICE for functional verification and performance analysis. The performance of the proposed ternary logic circuits is compared with the existing designs presented in the literature. The comparison results show that the propagation delay and circuit area of GNRFET‐based circuits are reduced with an average of 41.3 and 64%, respectively, than the existing ternary circuits.