Open AccessSizing of the CMOS 6T‐SRAM cell for NBTI ageing mitigation
Author(s) -
Chenouf Amel,
Djezzar Boualem,
Bentarzi Hamid,
Benabdelmoumene Abdelmadjid
Publication year - 2020
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2019.0307
Subject(s) - negative bias temperature instability , pmos logic , static random access memory , nmos logic , transistor , cmos , sizing , materials science , electronic engineering , mosfet , computer science , electrical engineering , optoelectronics , engineering , voltage , chemistry , organic chemistry
This study presents a negative bias temperature instability (NBTI) mitigation design technique for CMOS 6T‐static random access memory (6T‐SRAM) cells. The proposed approach is based on transistor sizing technique. It consists of sizing the nMOS access transistors of the cell to alleviate NBTI ageing occurring in its pMOS pull‐up transistors threatening the cell stability. Once the access transistors are sized for a better hold static noise margin under NBTI, the other transistors of the 6T‐SRAM cell could be properly sized for improved read stability and write‐ability.