Open AccessOn‐chip tunable Memristor‐based flash‐ADC converter for artificial intelligence applications
Author(s) -
Humood Khaled,
Mohammad Baker,
Abunahla Heba,
Azzam Anas
Publication year - 2020
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2019.0293
Subject(s) - flash adc , resistor , cmos , spice , computer science , electronic engineering , flash (photography) , linearity , analog to digital converter , memristor , voltage , chip , voltage reference , electrical engineering , engineering , physics , telecommunications , optics
This study presents a novel hybrid memristor (MR)‐complementary metal–oxide–semiconductor‐based flash analogue‐to‐digital converter (ADC). The speed and efficiency of the ADC are important aspects that can significantly affect the overall system performance. The flash ADC is considered the fastest type of ADCs; however, its performance is affected by the resistor mismatch. The proposed flash ADC is the first to use tunable MR to replace conventional resistor to generate accurate reference voltages. This is achieved by utilising the highly analogue behaviour observed in multi‐state MR devices fabricated and tested by the authors' group. The electrical parameters of the devices have been extracted by device characterisation, then the voltage‐threshold adaptive model (VTEAM) has been used to develop a correlated mathematical and Simulation Program with Integrated Circuit Emphasis (SPICE) device model. The proposed MR‐based flash‐ADC design solves the issue of resistor mismatch that results in encoding errors by the ability to tune the MR resistance value post‐processing. Moreover, being a nanoscale component, the usage of MR significantly improves the area efficiency of the target ADC. Furthermore, the proposed design has improved the ADC transfer function characteristic and has lower differential non‐linearity and integral non‐linearity errors compared with the conventional design.