Open Access9 ps TDC based on multiple sampling in 0.18 μm complementary metal–oxide–semiconductor
Author(s) -
Jin Shuowei,
Chai Jiaxin,
Li Jingjiao,
Yan Aiyun
Publication year - 2020
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2019.0242
Subject(s) - linearity , cmos , time to digital converter , signal (programming language) , sampling (signal processing) , interval (graph theory) , semiconductor device fabrication , electronic engineering , line (geometry) , resolution (logic) , materials science , computer science , clock signal , engineering , optoelectronics , mathematics , jitter , telecommunications , detector , geometry , combinatorics , wafer , programming language , artificial intelligence
A high‐precision measurement method, based on multiple sampling, is proposed for the time interval of two signals in this study. A time interval measurement circuit integrated into the time‐to‐digital converter (TDC), is designed based on this high‐precision measurement method. In the TDC, the authors use two identical delay lines as the holding module to ensure the two signals with a constant time interval. The TDC samples the two signals multiple times by a clock signal, whose period is shorter than that of the delay line. Consequently, the problem of limited resolution caused by a mismatch between delay lines in the delay‐line structure can be avoided, and the precision of the output can be improved. The proposed TDC is designed and simulated in Semiconductor Manufacturing International Corporation (SMIC) 0.18 μm complementary metal–oxide–semiconductor process. Simulation results show that the differential non‐linearity and the integral non‐linearity are always less than one least significant bits. The proposed TDC achieves input dynamic range of 0–32.13 ns and time resolution of 9 ps.