Open AccessInteger‐ N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector
Author(s) -
Koithyar Aravinda,
Ramesh Telugu Kuppushetty
Publication year - 2020
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2019.0189
Subject(s) - phase locked loop , charge pump , phase frequency detector , ring oscillator , voltage controlled oscillator , phase detector , pll multibit , lock (firearm) , voltage , detector , phase (matter) , physics , power (physics) , electrical engineering , loop (graph theory) , control theory (sociology) , electronic engineering , engineering , computer science , mathematics , mechanical engineering , control (management) , quantum mechanics , combinatorics , artificial intelligence , capacitor
In this article, a novel design is presented, for an Integer‐ N charge pump phase locked loop (PLL). The design is with a resetless phase frequency detector, and with the differential design of charge pump. The voltage‐controlled oscillator is of current starved type. The proposed PLL is not having any blind zone and is having near‐zero dead zone. When compared to the conventional design, the current mismatch in the charge pump is reduced by 3.21%, and the lock time of the PLL is reduced by 79%. The PLL is intended for 2.4 GHz application, and the obtained lock time is 1.7 μs. The implementation is done with the three‐stage ring oscillator, with divider of modulus as 24, in 180 nm TSMC technology. At 1.8 V supply voltage, the circuit consumes 9.72 mW of power.