Open AccessHigh throughput FIR filter architectures using retiming and modified CSLA based adders
Author(s) -
Patali Pramod,
Thottathikkulam Kassim Shahana
Publication year - 2019
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2019.0130
Subject(s) - retiming , adder , power–delay product , finite impulse response , computer science , throughput , filter (signal processing) , booth's multiplication algorithm , carry save adder , computer hardware , parallel computing , electronic engineering , algorithm , engineering , telecommunications , wireless , computer vision , latency (audio)
A methodology to improve the throughput of FIR filters through the effective use of retiming and efficient add–multiply operation is presented in this study. Delay, energy and area efficient linear and square root carry‐select adder (CSLA) structures are obtained by combining modified forms of carry look‐ahead and carry‐skip adder concepts to concatenated CSLA modules. The computational speed is enhanced by the quick generation and transmission of the end module carries by the module carry generation blocks. The delay performance of booth multiplier is improved by performing the partial product addition using the proposed square root CSLA. Two versions of the proposed filters are (a) high throughput low power and low complex retimed FIR filter and (b) high throughput energy efficient retimed FIR filter. The critical path delay, power, power–delay product and area–delay product of the proposed filter‐2 are reduced by 71, 38, 82 and 78%, respectively, with respect to flexible retimed filter and by 40, 11, 47 and 37%, respectively, with respect to modified transpose form filter for a filter length of 64. Cadence software with gpdk 45 nm standard cell library is used for the design and implementation.