Open AccessThree‐state dynamic random‐access memory (DRAM)
Author(s) -
Karmakar Supriya
Publication year - 2020
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2019.0117
Subject(s) - dram , dynamic random access memory , computer science , random access , random access memory , integrated circuit , memory cell , process (computing) , universal memory , state (computer science) , transistor , semiconductor memory , computer hardware , embedded system , computer memory , memory refresh , electrical engineering , engineering , operating system , algorithm , voltage
This work shows the design of three‐valued dynamic random‐access memory (DRAM) cell using quantum dot gate field effect transistor. DRAM is very popular for increasing device integration in integrated circuits. Storing multiple numbers of bits in a single DRAM cell increases the device integration further. The process technology is compatible with the conventional silicon process. The various write and read operations of the three‐value DRAM cell are also discussed in this work.