Open AccessIL analysis for 8‐way power combining network in 77–110 GHz 40 nm‐complementary metal–oxide–semiconductor PA design
Author(s) -
Huang ChingYing,
Wu PinHsuan,
Wu KunLong,
Hu Robert,
Chang ChiYang
Publication year - 2019
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2019.0074
Subject(s) - materials science , optoelectronics , electrical engineering , amplifier , transmission line , capacitor , insertion loss , cascode , electric power transmission , stub (electronics) , return loss , electrical impedance , voltage , cmos , engineering , antenna (radio)
In this study, the authors will investigate the insertion loss (IL) of the broadband 8‐way power combiner used in their millimetre‐wave power amplifier (PA) design. By treating this combiner as impedance transformer under resistor‐capacitor (RC)‐loading condition, both the characteristic impedance and electrical length of the constituting metal lines can be obtained, where the much shorter line length suggests wider bandwidth and lower IL. However, proper loss analysis must take into account the multi‐reflection of voltage wave along these mismatched transmission lines, i.e. the use of the power attenuation expression e − 2 α Lis just not accurate enough. With their derived equations, it shows that the IL of their proposed 8‐way combiner can be as low as 0.92 dB at 94 GHz, which is much smaller than the 1.5 dB for the conventional quarter‐wavelength combiner. Mathematics for the IL of the drain‐bias shunt stub and the output DC‐blocking capacitor has also been derived. As a demonstration, a 77–110 GHz 40 nm‐complementary metal–oxide–semiconductor PA made of cascode transistors is then designed that has more than 18 dB gain, and its OP1 dB is around 13 dBm across the whole frequency range.