12 bit 3.072 GS/s 32‐way time‐interleaved pipelined ADC with digital background calibration for wideband fully digital receiver application in 65 nm complementary metal–oxide–semiconductor

The performance of a wideband receiver is highly dependent on the performance of the analogue‐to‐digital converter (ADC) used. Such applications require ADCs to operate at ultra‐high speeds with high accuracy for inputs ranging from 40 MHz ‐ 1 GHz. Conventional solutions either use filters and mixers to extract the frequency of interest and convert it using a low‐speed ADC or use a single ultra‐high‐speed flash converter. Both of these solutions consume ultra‐high power and require complex circuitry, which expands exponentially with the converter resolution. In this work, a 12 bit 3.072 GS/s time‐interleaved pipeline ADC is proposed. In total, 32 pipeline ADCs, each with a sampling rate of 96 MS/s, are interleaved in the time domain to achieve an overall sampling rate of 3.072 GS/s. In addition to the potential energy‐saving capabilities of a time‐interleaving structure, the circuit adopts amplifier sharing in sample‐and‐hold circuits, further improving the power efficiency. To account for interleaving mismatch, the circuit uses a pure background calibration technique, maintaining the system linearity and spectral efficiency. The proposed design achieves signal‐to‐noise‐and‐distortion ratio of 53.65 dB and spurious‐free dynamic range (SFDR) of 69.04 dB while consuming 820 mW of power at a 1.2 V supply, resulting in a figure‐of‐merit of 0.67 pJ/conv‐step.