Open AccessGray‐code adder with parity generator – a novel quantum‐dot cellular automata implementation
Author(s) -
Vieira Luiz G.L.,
Vieira Luiz F.M.,
Vieira Marcos A.M.,
Vilela Neto Omar P.
Publication year - 2020
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2019.0003
Subject(s) - adder , computer science , quantum dot cellular automaton , cmos , cellular automaton , gray code , encoder , parity bit , computer hardware , electronic engineering , computer architecture , embedded system , algorithm , engineering , operating system
This study describes the first Gray‐code adder architecture, without the need to transform the Gray code into binary code, using the quantum‐dot cellular automata (QCA). This device is a widely used resource for machine communications, counters, and encoders. QCA is a possible alternative to the current integrated circuit [complementary metal oxide semiconductor (CMOS)] due to its nanometric scale and very low‐power consumption. In a bottom‐up approach, the authors first describe and present the architecture of an important building block that composes the Gray‐code adder, the parity generator, and then describe the full architecture. Besides being essential in the proposed adder, the parity generator is also important for error‐checking and construction of other devices and widely used in communications. They demonstrate the functionality, test, and validate the proposed architectures using the QCADesigner simulator. If QCA consolidates as a possible CMOS substitute, this study can impact the design of future components that uses Gray‐code and parity generator, such as embedded digital communications systems that will benefit from the low‐power consumption of the QCA technology.