Open AccessArchitecture‐aware routability‐driven placer for large‐scale mixed‐size designs
Author(s) -
Datta Prasun,
Mukherjee Shyamapada
Publication year - 2019
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2018.5518
Subject(s) - benchmark (surveying) , placement , computer science , routing (electronic design automation) , block (permutation group theory) , parallel computing , cluster analysis , very large scale integration , electronic circuit , placer mining , adder , physical design , computer engineering , algorithm , circuit design , embedded system , engineering , mathematics , telecommunications , geometry , geodesy , machine learning , electrical engineering , geography , latency (audio) , materials science , metallurgy
In this study, the authors have presented a simple but robust routability‐driven placement for the mixed‐size designs. The proposed technique is implemented through (i) look‐ahead legalisation‐based global placement, (ii) congestion removal and (iii) detailed placement stages. A balanced clustering technique has been proposed to group the circuit blocks into clusters based on the types of circuit blocks and their connectivity. A 0‐1 integer programming‐based global placement method is framed, which performs look‐ahead legalisation. A new site information table concept is introduced to keep the information about each placement cell. Based on the divide conquer strategy, placement area is divided into a region to reduce problem size. A force‐directed method has been conceived to select an appropriate region for global placement for the blocks of a cluster. A new congestion removal approach substitutes the legalisation stage to remove circuit block congestion and pin density in different regions. Finally, a gain‐based strategy has been introduced for routability‐driven detailed placement. The proposed technique is implemented and tested on ICCAD 2012 benchmark circuits. It achieves 1.92 and 0.13% improvements in terms of half perimeter wirelength and routing congestion w.r.t. recent placers.