Open Access1.2 V 10‐bits 40 MS/s CMOS SAR ADC for low‐power applications
Author(s) -
Lu ChiChang,
Huang DingKe
Publication year - 2019
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2018.5512
Subject(s) - successive approximation adc , spurious free dynamic range , cmos , linearity , capacitor , integral nonlinearity , differential nonlinearity , electronic engineering , least significant bit , electrical engineering , dynamic range , figure of merit , voltage , computer science , physics , engineering , converters , optoelectronics , operating system
This article presents a 10‐bits low‐power successive approximation register analogue‐to‐digital converter (SAR ADC). The dual sampling technique was applied to the capacitive digital‐to‐analogue converter (CDAC), and the CDAC structure was constructed using a binary‐weighted capacitor array and a C‐2C capacitor array, simultaneously. Consequently, the CDAC structure enabled low‐power consumption and a small layout area for the proposed SAR ADC. Moreover, the rail‐to‐rail operation of the bootstrapped circuit enabled the low‐voltage ADC to be implemented, thereby improving the non‐linearity. A prototype was designed and implemented using TSMC 0.18 μm CMOS 1P6M technology. This design achieved differential non‐linearity and integral non‐linearity of 0.36 least significant bit (LSB) and 0.45 LSB, respectively, and a signal‐to‐noise‐and‐distortion ratio of 56.7 dB and spurious‐free dynamic range of 65.8 dB at the input frequency of 2 MHz. At a sampling rate of 40 MS/s with a single 1.2 V power supply, the power consumption was 736 μW. The proposed ADC achieved a figure‐of‐merit of 32.84 fJ/conversion‐step. The ADC core occupied an active area of 195 × 241 μm 2 .