Open AccessApproach for low power high speed 4‐bit flash analogue to digital converter
Author(s) -
Razavi Bagher,
Tavakoli Mohammad Bagher,
Setoudeh Farbod
Publication year - 2020
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2018.5504
Subject(s) - bit (key) , flash (photography) , power (physics) , computer science , flash adc , 4 bit , analog to digital converter , computer hardware , arithmetic , electrical engineering , engineering , mathematics , physics , optics , quantum mechanics , voltage , computer security , voltage reference , cmos
In this study a new structure was presented to design and simulate a considerably low power and high‐speed 4‐bit flash analogue to digital converter based on TSMC 0.18 µm complementary metal‐oxide semiconductor (CMOS) technology. In this structure, in order to reduce the power consumption in the proposed comparator, the reference voltage was removed and replaced with the threshold voltage of CMOS transistors. This method has reduced the power consumption greatly. Additionally, by employing reversible logic in the 2:1 multiplier, the power consumption and the number of stages were dropped and obtaining a faster converter was considered as the other breakthrough. The simulation was carried out in 1.8 V supply voltage and power consumption of 330 µW while the sampling rate was equal to 2GSample/s.