Open AccessNear threshold voltage digital PLL using low voltage optimised blocks for AR display system
Author(s) -
Jun Jaehun,
Lee Sangsu,
Kim Chulwoo
Publication year - 2020
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2018.5468
Subject(s) - jitter , voltage , digitally controlled oscillator , dpll algorithm , phase locked loop , cmos , voltage controlled oscillator , power (physics) , low voltage , low power electronics , electrical engineering , electronic engineering , materials science , computer science , engineering , power consumption , physics , delay line oscillator , quantum mechanics
In this work, a digital phase‐locked loop (DPLL) is proposed for the low power and stable operation in an augmented reality (AR) display system. The AR display system which needs the ultra‐low power consumption adopts the near‐threshold voltage (NTV) operation in both digital and analogue blocks. The NTV region has the advantage of small power dissipation with low‐supply voltage. However, it suffers from performance degradation due to a large delay, slow transition time, and small dynamic voltage range. To achieve the optimised power efficiency and stable performance, the dynamic time‐to‐digital converter and the low voltage optimised digitally controlled oscillator are applied in the proposed DPLL. In addition, the forward body biasing scheme is used to increase the operation frequency for the sigma‐delta modulator block. The proposed DPLL is fabricated using 65 nm CMOS technology and shows a current consumption of 160 μA at a voltage of 0.55 V. In addition, the jitter characteristic shows 6.7 ps rms jitter and 50 ps peak to peak jitter at 480 MHz.