Open AccessEfficient and high‐throughput application‐specific integrated circuit implementations of HIGHT and PRESENT block ciphers
Author(s) -
Rashidi Bahram
Publication year - 2019
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2018.5457
Subject(s) - computer science , adder , throughput , parallel computing , block cipher , critical path method , block (permutation group theory) , cmos , computer hardware , s box , computer architecture , arithmetic , latency (audio) , cryptography , algorithm , electronic engineering , mathematics , engineering , geometry , wireless , telecommunications , systems engineering
In this study, low‐cost and high‐throughput hardware implementations of the HIGHT (HIGh security and lightweigHT) and PRESENT lightweight block ciphers are presented. One of the most complex blocks in the HIGHT algorithm is addition modulo 2 8 . In the proposed structure for implementation of this modular adder, the authors used the structure of Ladner‐Fischer, Han‐Carlson, Kogge‐Stone and Sklansky adders, which are parallel prefix adders with low critical path delay and suitable hardware resources. In the PRESENT block cipher, for two key lengths 80‐bit and 128‐bit, the S‐box is implemented based on an area‐optimised combinational logic circuit. In the proposed S‐box structure, the number of logic gates and critical path delay is reduced by using Karnaugh mapping and further factorisation. Also, to reduce the latency and increase throughput, the loop unrolling technique is applied in the structures. Implementation results of the proposed architectures in 180 nm complementary metal–oxide–semiconductor technology for different unroll factors are achieved. The results show improvements in terms of execution time, throughput and throughput/area compared to other related works.