Open AccessAssessment of interface traps in In 0.53 Ga 0.47 As FinFET with gate‐to‐source/drain underlap for sub‐14 nm technology node to impede short channel effect
Author(s) -
Pathak Jay,
Darji Anand
Publication year - 2019
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2018.5319
Subject(s) - materials science , threshold voltage , optoelectronics , node (physics) , subthreshold conduction , subthreshold swing , mosfet , work function , electrical engineering , transistor , voltage , physics , nanotechnology , engineering , quantum mechanics , layer (electronics)
Silicon fin field‐effect transistor (FinFET) devices with gate–source/drain underlap fin length ( L un ) structures have been used for effective reduction in short channel effects (SCEs) from many years. Here, investigations have been performed on the FinFET structure with In 0.53 Ga 0.47 As material. Three‐dimensional technology computer‐aided design simulations for 14 nm channel length In 0.53 Ga 0.47 As FinFETs with underlap have been conducted by incorporating various effects to analyse the influence of interface traps on the device. The dominance of traps is investigated on SCE and intrinsic delay to assess the trend on underlap devices. The impact on threshold voltage and on current due to metal gate work function (MGWF) variation has been also demonstrated. Simulations have been carried out for L un = 0, 3, 6, and 9 nm with interface trap density of 10 12 and 10 14 cm –2 eV –1 . Improvement in the subthreshold swing (SS) is observed as the L un increases but at the cost of intrinsic delay. However, the improvement in SS after L un = 6 nm is nearly constant. It has been also observed that the relative standard deviation of the threshold voltage and on current variation due to MGWF variation improves as the L un increases till 6 nm after that this improvement is not very significant.