Open AccessAll‐digital delay line‐based time difference amplifier in 65 nm CMOS technology
Author(s) -
Razmdideh Ramin,
Saneei Mohsen
Publication year - 2019
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2018.5304
Subject(s) - cmos , amplifier , electronic engineering , time to digital converter , line (geometry) , electrical engineering , chip , voltage , power (physics) , computer science , engineering , physics , mathematics , electronic circuit , geometry , quantum mechanics , clock signal
Time‐to‐digital converter (TDC) is one of the important blocks in most of the digital systems that need to have high resolution. Time difference amplifier (TDA) is used in TDC for increasing the resolution. In this study, an all‐digital TDA is proposed. The proposed TDA uses the delay lines with difference delay for amplifying. The proposed circuit is designed and simulated in 65 nm CMOS technology and has a gain of ten and a chip area of about 0.003 mm 2 . The calculated maximum gain error is 5%. The proposed TDA consumes 0.94 mW power under 1.1 V supply voltage.