Open AccessAnalytical modelling of dielectric engineered strained dual‐material double‐gate‐tunnelling field effect transistor
Author(s) -
Kumar Dash Dinesh,
Saha Priyanka,
Kumar Sarkar Subir
Publication year - 2019
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2018.5293
Subject(s) - quantum tunnelling , electric field , tunnel field effect transistor , dielectric , gate oxide , gate dielectric , field effect transistor , materials science , optoelectronics , transistor , drain induced barrier lowering , electrical engineering , physics , engineering , voltage , quantum mechanics
In this endeavour, the fruition of a resurrected tunnel field effect transistor has been investigated incorporating the idea of strained channel engineering along with the implementation of dielectric modulation technique. A non‐homogeneous pattern of gate oxide layer is considered with hetero‐dielectric architecture at the front gate and linearly graded oxide at the back gate. The buried oxide (BOX) thickness is kept intentionally double that of front oxide one to reduce electric field lines penetrating from drain to source, thus minimising fringing field effect. The surface potential function has been deduced with the help of 2D Poisson's equation assuming appropriate boundary conditions. Lateral electric field and hence total electric field have been computed from channel potential to study tunnelling efficiency, hot carrier effect and drain induced barrier lowering for the aimed device. Finally drain current has been derived with the help of Kane's model upon integration of band‐to‐band tunnelling rate and the results have been compared with previously published reports to corroborate the eminence of the proposed model. All analytical corollaries are in adroit amity with Silvaco ATLAS simulated data for avowal of the developed modelin terms of sublime short channel behaviour.