Open AccessHardware architectures for PRESENT block cipher and their FPGA implementations
Author(s) -
Pandey Jai Gopal,
Goel Tarun,
Karmakar Abhijit
Publication year - 2019
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2018.5273
Subject(s) - computer science , datapath , block cipher , embedded system , advanced encryption standard , field programmable gate array , encryption , cipher , cryptography , aes implementations , virtex , triple des , computer hardware , computer architecture , computer network , algorithm
Data security is essential for the proliferation of the Internet of things and cyber‐physical system technologies. Data security can be efficiently achieved by incorporating lightweight cryptography techniques. In this study, a set of high‐performance hardware architectures for PRESENT lightweight block cipher are proposed that perform encryption, decryption and integrated encryption/decryption operations. Datapath of the architectures is of 64 bit width that supports standard 80 and 128 bits key lengths. The architectures are synthesised on Xilinx Virtex‐5 XC5VLX110T (ff1136‐1) field‐programmable gate array device of ML‐505 platform. To perform functional verification, a large number of test vectors are used. Performance measurement is performed by evaluating maximum frequency, throughput, power dissipation and energy consumption. Experimentally, it is found that the proposed architectures are resource‐efficient, high‐performance and suitable for lightweight, latency‐critical and low‐power applications in comparison with existing architectures.