High‐Q second‐order all‐pass delay network in CMOS

Analogue signal processing (ASP) is a promising alternative to digital signal processing techniques in future telecommunication and data‐processing solutions. Second‐order all‐pass delay networks – the building blocks of ASPs – are currently primarily implemented in off‐chip planar media, which is unsuited for volume production. In this study, a novel on‐chip complementary metal–oxide–semiconductor (CMOS) second‐order all‐pass network is proposed that includes a post‐production tuning mechanism. It is shown that automated tuning with a genetic local optimiser can compensate for CMOS process variation and parasitics, which make physical realisation otherwise infeasible. Measurements indicate a post‐tuning bandwidth of 280 MHz, peak‐to‐nominal delay variation of 10 ns and magnitude variation of 3.1 dB. This is the first time that measurement results have been reported for an active inductorless on‐chip second‐order all‐pass network with a delay Q‐value larger than 1.