Open AccessFast digital foreground gain error calibration for pipelined ADC
Author(s) -
Kaur Jupinder,
Prabhakar Prince,
Singh Anil,
Agarwal Alpana
Publication year - 2019
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2018.5230
Subject(s) - spurious free dynamic range , calibration , computer science , dynamic range , successive approximation adc , linearity , least significant bit , differential nonlinearity , distortion (music) , algorithm , field programmable gate array , noise (video) , electronic engineering , mathematics , computer hardware , amplifier , artificial intelligence , comparator , electrical engineering , statistics , telecommunications , computer vision , bandwidth (computing) , voltage , engineering , image (mathematics) , operating system
Here, a fast digital foreground calibration technique to calibrate the gain error in the pipelined analogue‐to‐digital converter (ADC) is proposed. The technique suggested uses maximum reference value of the ADC along with least mean squares adaptive algorithm to compensate the gain error. It avoids the use of slow but accurate reference ADC, thus saving area, power, and design efforts. The proposed calibration algorithm is implemented in Xilinx Artix‐7 FPGA kit to show the effectiveness of the algorithm. After calibration, differential non‐linearity improves by 30% and integral non‐linearity reduces from values +60/−60 LSB to +0.77/–0.77 LSB. Also, signal to noise and distortion ratio and spurious‐free dynamic range improve significantly from 35.9193 and 36.7348 to 75.3619 and 82.2884 dB, respectively, after calibration.