Open AccessLDPC check node implementation using reversible logic
Author(s) -
Awais Muhammad,
Razzaq Anas,
Ahmed Ashfaq,
Masera Guido
Publication year - 2019
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2018.5222
Subject(s) - low density parity check code , computer science , decoding methods , schematic , transistor , power gating , logic gate , node (physics) , cmos , very large scale integration , electronic engineering , computer engineering , algorithm , embedded system , electrical engineering , voltage , engineering , structural engineering
Reversible logic is an emerging digital design paradigm which promises low energy dissipation; thanks to its information‐lossless nature. True potential of this exciting concept can only be assessed by facing the design of practical complexity applications. Low density parity check (LDPC) decoding is one such application from forward error correction domain. The core of LDPC decoding is the check node (CN) processor, which executes the decoding algorithm and constitutes a major portion of decoder's overall power consumption. This work proposes a low‐power LDPC CN architecture using reversible logic gates. Transistor level design and full custom layout of proposed architecture is carried out on UMC 90 nm complementary metal–oxide–semiconductor technology. All reversible blocks of proposed CN are optimised for quantum cost, garbage outputs and transistor count. The CN functionality is validated with post‐layout simulations, layout versus schematic checks and design rule checks. The proposed CN occupies a post‐layout area of 0.013 mm 2 , achieves up to 4.3 GHz frequency and consumes 52μ W power. The performance of proposed CN is also compared with its implementation using irreversible gates. The proposed CN achieves about 300% reduction in power delay product with affordable complexity as compared to its classical implementation.