Open AccessDFT processor implementation scheme based on Rader algorithm
Author(s) -
Samiha Aouissi,
Mohamed Benouaret,
Saliha Harize
Publication year - 2019
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2018.5200
Subject(s) - computer science , discrete fourier transform (general) , fast fourier transform , algorithm , prime (order theory) , latency (audio) , process (computing) , throughput , computation , discrete hartley transform , parallel computing , wireless , mathematics , fourier transform , telecommunications , mathematical analysis , fourier analysis , combinatorics , fractional fourier transform , operating system
The implementation of a discrete Fourier transform (DFT) algorithm plays a key role in many real‐time applications. This study mainly deals with the design and implementation of a DFT processor with non‐power‐of‐two (prime) problem sizes using the Rader algorithm. The proposed design focuses on increasing the speed to fulfil the requirements of the real‐time data transmission by enabling data rates up to 10 Gbps. Despite its limitation to the prime size, it remains a promising tool in the signal processing aspect and takes its place among other techniques to achieve high‐speed wireless communication. By avoiding the cumbersome process during twiddle factors computation as well as the butterfly structure, the outcome preludes to an ambitious architecture dedicated to high‐speed design reaching over 233 and 92 MHz for DFT lengths of 7 and 67, respectively, on Virtex 6. Thereby, the obtained results prove the efficiency of the algorithm and show the trade‐off to be established in terms of occupied area, throughput, latency, and power consumption.