Open AccessSi 3 N 4 :HfO 2 dual‐k spacer bulk planar junctionless transistor for mixed signal integrated circuits
Author(s) -
Garike Ramarao,
Patil Ganesh C.
Publication year - 2019
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2018.5168
Subject(s) - planar , materials science , transistor , integrated circuit , electronic circuit , dual (grammatical number) , signal (programming language) , optoelectronics , electrical engineering , computer science , engineering , voltage , art , computer graphics (images) , literature , programming language
For the first time halfnium oxide (HfO 2 ) is being incorporated in the dual‐k spacers and has been used in bulk planar junctionless transistor (BPJLT). It has been found that incorporating HfO 2 in spacers not only improves the electrostatic integrity but also improves digital/analogue circuit performance of the BPJLT. Further, the increased effective gate length due to fringing electric field through HfO 2 to thin body reduces OFF‐state leakage, subthreshold swing and drain‐induced barrier lowering by ∼60, ∼15 and ∼30%, respectively. Although the presence of HfO 2 inner spacer layer at source/drain increases the parasitic capacitances, the significant improvement in ON‐state drive current reduces the intrinsic gate delay of the device. Further, the analogue circuit figures of merit such as transconductance, transconductance generation factor and the intrinsic gain of the proposed device are found to be significantly improved over the conventional BPJLT device. The mixed mode device/circuit simulation results of an inverter and the common source amplifier show that leakage power dissipation, propagation delay and the open‐circuit voltage gain of the proposed device are improved significantly over the conventional BPJLT device. The fabrication process flow of this novel device has also been proposed.