Open AccessHighly‐digital voltage scalable 4‐bit flash ADC
Author(s) -
Gupta Ashima,
Singh Anil,
Agarwal Alpana
Publication year - 2019
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2018.5148
Subject(s) - flash adc , comparator , cmos , least significant bit , differential nonlinearity , spurious free dynamic range , successive approximation adc , linearity , inverter , computer science , electronic engineering , analog to digital converter , flash (photography) , electrical engineering , capacitor , voltage , physics , engineering , optics , operating system
This study describes the highly‐digital 4‐bit 200 MS flash analogue to digital converter (ADC) whose major part can be digitally synthesised thus achieving low power, reducing the time‐to‐market and is scalable with technology. The comparators used in the ADC consist of complementary metal–oxide–semiconductor (CMOS)‐based inverter and NAND‐NOR as standard cells. The complete flash ADC is designed in 180 nm CMOS technology with 1.8 V supply with the power consumption of 4.51 mW. The signal‐to‐noise and distortion ratio, signal‐to‐noise ratio and spurious‐free dynamic range are equal to 23.3, 25.2 and 30.1 dB. It provides an effective number of bits equal to 3.5. The differential non‐linearity (DNL) of this ADC is ± 0.25 LSB and integral non‐linearity (INL) is + 0.6 LSB.