Open AccessHardware implementation of the quasi‐maximum likelihood estimator core for polynomial phase signals
Author(s) -
Brnović Nevena R.,
Djurović Igor,
Ivanović Veselin N.,
Simeunović Marko
Publication year - 2019
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2018.5112
Subject(s) - estimator , algorithm , polynomial , computer science , field programmable gate array , gate array , software , computer engineering , computer hardware , electronic engineering , mathematics , engineering , statistics , mathematical analysis , programming language
Flexible, multiple‐clock‐cycle, hardware design for the quasi‐maximum likelihood (QML) algorithm core realisation for the polynomial phase signals (PPSs) estimation is proposed. The QML algorithm significantly outperforms existing PPS estimators in terms of accuracy. However, its practical applications require efficient software and hardware systems. The main challenges in the proposed hardware development with respect to existing systems for time–frequency (TF) analysis are realisation of TF representation based instantaneous frequency estimator, the polynomial regression, and phase extraction. The developed design is tested on a PPS corrupted by a white Gaussian noise and verified by a field programmable gate array circuit design. All implementation and verification details are provided along with the comparison of the results achieved by hardware and software implementations.